• Home

APB

various APB related code examples.
  FPGA proven NO
  ASIC proven NO

Introduction

The ARM^® APB interface is used by many IP providers. In this directory you will find various APB related code examples. It also contains a behavioural module which can generate APB bus cycles. The docs directory has a short description but also a copy of the ARM APB AMBA specification.
In the archive you find the following apb modules:

• apb_regs.v           Basic read and write code
• apb_regs1.v         Small variant on the previouos
• apb_wrtsetclr.v   Write-to-set and write-to-clear register
• apb_pulse.v         Generate pulses from read and writes
• apb_fifo.v             Example of a 256x8 FIFO
• apb_levirq.v         Control/enable incoming level interrupts
• apb_edgeirq.v     Control/enable edge interrupts
• apb_decode.v     APB address decoder
• apb_fastdecode.v Faster and smaller version of the above
• apb_bus.v           Behavioural apb bus module

The code can be found here. A document describing the code (initial release) is available here.
As usual the code comes complete with the test benches I used to verify the operation. In this case the test-benches are NOT self-checking.