Added: 18-04-2020, SPI salve.
A very small SPI slave interface.
Added: 18-01-2017, Clock mux. A safe way to multiplex two clocks.
Added: 23-01-2017, Crystal startup. A circuit which passes a crystal clock after it has stabilised.
Added: 27-01-2017, System Reset. How to avoid reset_tree balancing
For all three follow the link: Clock and reset control
Added: 28-02-2017, AHB SRAM interface. Connect synchronous memory to an AHB bus without incurring wait cycles
Follow the link: AHB
Added: 9-10-2017, AXI mux/arbiter with test IP. A number of absolute minimum size multiplexors for two, three ... five AXI slaves into one AXI master with round-robin or static priority.
Added: 24-10-2017, 25-10-2017, AXI 2-, 3-, and 4-port splitter. Added: 25-10-2017, AXI decode error handling module. Here is the link: AXI
There are two odd-even sort network modules. Both are purely combinatorial
thus the sorting takes place in one clock cycle. From both the data width and the number
of input ports can be set using parameters.
For these modules the number of input ports must be a power of two.
- sort_N sorts N input ports of W bits wide.
- maxmin_N finds the maximum and minimum of N input ports W bits wide
Here is the link: Sorting
In this Verilog website I hope to offer some things others don't have.
There are many Verilog examples and tutorial web sites but few have complete free modules you can download. Let alone the test benches (from which you can often learn more than the code itself). All code snippets and modules given as example are provided completely free. There are no restrictions to any use or re-use of this code in any form or shape. Which also means the user is free to modify the code. It would be nice if you keep my company name 'Fen Logic Ltd.' in the source or modified source code but even that is not required as I can't check it anyway. But the code comes with no warranties or guarantees whatsoever.
Most websites offer you the standard circuitry (FIFO, UART, Synchroniser). Yes, you find some of those here too, but this website also deals with the more exotic and complex pieces of Verilog coding. For example all the other websites assume that you have a clean clock (or clocks) and a nicely behaving reset. However those do not appear by themselves. In this website I plan to offer you some of these more exotic and notorious circuits.
I have dealt with ARM (c) processors for most of my twenty years. I have dropped in the old ARM7, ARM1176, ARM9 (FPGA only), Quad A7 and assisted with a Quad A53. In the next year I hope to provide interface circuits for the AMBA bus interface and if I have some time left I might drop the occasional AXI infrastructure component.
This website offers you advice and experience gathered in more
then twenty years of writing Verilog code. Some of it is personal
preference but most of it has been learned the hard way.
If I seem to do something 'overly complex' there is likely a reason for it.
The website is far from complete. I plan to spend a lot more time in the next year on it so please bear with me. For now I strongly suggest you do not link to any of the sub-pages as they will all be moving around when I get around to categorising them.
As you can see there are no adverts. Neither are there any cookies. I hope to keep it that way.
For questions or contract work email me: