Clocks and Reset
As mentioned on the main page, most (all?) Verilog examples assume that you have a clean clock and a nicely behaving reset. However those do not appear by themselves. This is the first deliverable of the more exotic circuits: a clock multiplexor. As with a lot of exotic code: the code looks deceptive simple. However tempting it may be to 'improve' on this, there is the risk of invalidating
Clock mux
The clock mux is a circuit which selects (multiplexes) one of two clocks. The challenge is to generate an output clock which is glitch free. This module offers that service with the caveat that the clock select signal does not change too fast (See the doumentation and the code).
Pointers:
Crystal startup delay
The start-up of the oscillation is depending on electric noise. As a consequence
of this, the crystal start-up time is non-deterministic. It depends on the
circuit in which the device is placed, the type and amount of decoupling and
very much on the way the power comes up . Therefore when power is applied to a
crystal oscillator the time before the crystal is producing a regular clock is
unknown.
The module xtal_startup.v takes care of all the difficulties of that process.
The circuit is designed to cope with irregular clock pulses. It waits for a time
and will pass the input clock on to the output after a number of valid clock
pulses have been seen. The crystal is assume to be stable after that delay.
There are three version. Read the documentation why.
Pointers:
- xtal_startup.v.
- xtal_startup2.v.
- xtal_startup3.v.
- xtal_startup_test.v.
- DregNegclk.v.
- xtal_startup2_test.v.
- DregNegSet.v.
- xtal_startup3_test.v.
- Dreg.v.
System Reset
The presented circuit makes the balancing of the reset tree with the
clock tree superfluous. That saves silicon area and reduced time and
effort in the layout team.
Pointers: