SPI slave

A mininal sized SPI slave interface.
    FPGA proven NO
    ASIC proven NO


This is the implementation of a very simple SPI slave interface. It can be used where registers are at a premium, e.g. a CPLD. This design uses 24 registers,

The design does NOT need any clock or reset signals alongside the standard SPI signals. However it uses both the spi_clk as well as the spi_cs_n signals to clock registers. (This means ideally these signals should drive a dedicated FPGA/CPLD clock pin)
The design does not require any other clock or reset, however this also implies that arriving data is dealt with a-synchronously. That means you will have meta stability when the arriving data is changing at the same time that it is read. In the archive you find the following modules:

The code can be found here
As usual the code comes with test benches, in this case a self-checking testbench.

A document describing the SPI slave module is forthcoming.