FIFOs
A set of standard FIFOs.
  FPGA proven NO
  ASIC proven NO
Introduction
FIFOs are one of the common building blocks of ASIC design.
A-synchronous FIFOs are essential to pass data between clock domains.
Synchronous FIFOs offer data flow decoupling between modules.
All FIFOs have parameters to control the data width and the FIFO depth.
In the archive you find several FIFOs:
- sync_fifo.v           My most used synchronous FIFO, depth is a power of two
- sync_fifo1.v         Slightly smaller (but slower) variant
- sync_fifo2.v         Like sync_fifo but aribtrary depth
- sync_fifo_hd.v     FIFO with halved output data width (e.g. 16 → 8 bits)
- sync_fifo_dd.v     FIFO with doubled output data width (e.g. 8 → 16 bits)
- async_fifo.v         My most used a-synchronous FIFO
- async_fifo_lib.v   A-synchronous FIFO with library cells for synchronisers
The code can be found
here.
A document describing the FIFO(s) (initial release) is available
here.
As usual the code comes complete with the test benches I used to verify the operation.