A set of standard FIFOs.
  FPGA proven NO
  ASIC proven NO


FIFOs are one of the common building blocks of ASIC design. A-synchronous FIFOs are essential to pass data between clock domains. Synchronous FIFOs offer data flow decoupling between modules. All FIFOs have parameters to control the data width and the FIFO depth. In the archive you find several FIFOs:

The code can be found here. A document describing the FIFO(s) (initial release) is available here.
As usual the code comes complete with the test benches I used to verify the operation.